../../../MVU/verification/ip/xilinx/bram64k_64x1024_xilinx.v
../../../MVU/verification/ip/xilinx/bram2m_xilinx.v
../../../MVU/verification/tests/3RD_PARTY_IP/rtl/altera_mf.v
../../../MVU/verilog/bram64k.v
../../../MVU/verilog/bank64k.v
../../../MVU/verilog/bram2m.v
../../../MVU/verilog/cdru.v
../../../MVU/verilog/cdwu.v
../../../MVU/verilog/maxpool.v
../../../MVU/verilog/mvp.v
../../../MVU/verilog/mvu.v
../../../MVU/verilog/shacc.v
../../../MVU/verilog/vvp.v
../../../MVU/verilog/interconn.v
../../../MVU/verilog/quantser.v
../../../MVU/verilog/quantser_ctrl.v
../../../MVU/verilog/outagu.v
../../../MVU/verilog/inagu.v
../../../MVU/verilog/agu.v
../../../MVU/verilog/fixedpointscaler.v
../../../MVU/verilog/zigzagu.v
../../../MVU/verilog/controller.v
../../../MVU/verilog/shiftreg.v
../../../MVU/verilog/mvutop.v
../../../pito_riscv/vsrc/rv32_defines.svh
../../lib/utils/rv32_pkg.sv
../../lib/utils/pito_pkg.sv
../../lib/utils/utils.sv
../../lib/utils/rv32_utils.sv
../../../pito_riscv/vsrc/rv32_instr.svh
../../../pito_riscv/vsrc/rv32_imm_gen.sv
../../../pito_riscv/vsrc/rv32_decoder.sv
../../../pito_riscv/vsrc/bram_32Kb.v
../../../pito_riscv/vsrc/rv32_data_memory.sv
../../../pito_riscv/vsrc/rv32_instruction_memory.sv
../../../pito_riscv/vsrc/rv32_alu.sv
../../../pito_riscv/vsrc/rv32_regfile.sv
../../../pito_riscv/vsrc/rv32_barrel_regfiles.sv
../../../pito_riscv/vsrc/rv32_core.sv
../../../pito_riscv/vsrc/rv32_next_pc.sv
../../../pito_riscv/vsrc/rv32_csr.sv
../../../pito_riscv/vsrc/rv32_barrel_csrfiles.sv
../../../vsrc/accelerator.sv
./accel_tester.sv